1. Field of the Invention
The present invention relates to a wafer alignment mark for image processing, an image processing alignment method using the wafer alignment, and a method of manufacturing a semiconductor device.
2. Description of the Related Art
Conventionally, as shown in FIG. 12, wafer alignment marks 1 and 1 for achieving fine alignment in X- and Y-directions are disposed in scribe regions in the X- and Y-directions of each shot 2 provided on a wafer 3.
Typically, used as the wafer alignment mark 1 for the image processing is a box-type pattern with 6 μm in lateral dimension and 30 μm in longitudinal dimension in its external shape or an L/S mark of frame-type pattern, in which a plurality of lines (about seven to nine) are provided at about 6 μm intervals.
If the wafer alignment mark 1 for image processing is formed to have the originally designed dimensions, the alignment accuracy can be maintained.
However, in general, there is often a gap between the shape or dimension of the wafer alignment mark 1, which has gone through various semiconductor manufacturing processes, and the designed values of the device. Therefore, there may face problems such as errors in alignment measurement due to deformation, asymmetry, variations in the processes and the like.
In order to suppress the problem such as the error in the alignment measurement to a minimum, it is desirable to provide a plurality of wafer alignment marks 1 by every process.
However, in general, there are twenty or more steps in lithography and, at the same time, there is a limit for the area used as scribe regions. Therefore, it has been extremely difficult to provide a plurality of wafer alignment marks corresponding to all the process.